The performance of an integrated circuit may be determined by the clock frequency at which it operates. Generally, electronic design automation (EDA) tools are used by circuit designers or design engineers to create circuit designs (commonly referred to as user designs) on integrated circuit devices. When designing a circuit, a circuit designer or design engineer may perform various operations using the EDA tool to validate the circuit design. This includes, among others, a timing analysis operation that is used to compute the expected timing of the circuit design without running actual circuit simulations.
Such timing operations may be commonly known as timing analysis. When a timing analysis is performed, every path or connection that couples one logic element to another in the circuit design may be evaluated. A typical timing analysis may produce two values for each analyzed path, namely, setup margin and hold margin. The setup margin of a particular signal path refers to the margin (or time period) available on the path for which a signal travelling through the path has to be stable before the arrival of its corresponding clock signal. The hold margin refers to the margin available on the signal path for which the same signal has to be stable after the arrival of its corresponding clock signal.
Generally, delays on respective paths on an integrated circuit may be modeled as a range of delays with a minimum value and a maximum value. Different delay values are typically used in the timing analysis. Depending on the delay values used, timing margins provided by the timing analysis may be overly pessimistic. For instance, when modeling transistor aging effects on a circuit design, the resulting timing analysis may be overly pessimistic when the circuit design is modeled solely based on a worst-case scenario (e.g., by increasing a maximum delay by an aging factor) without considering other factors such as the static probability of the path being analyzed.